C++ Low Latency Developer

Open Systems Technologies is a national provider of smart staffing solutions, providing contract staffing, permanent placements and executive searches in the following skill areas:

- Technology

- Finance, Accounting, and Operations

- Government Services

- Legal

- Global Services

Established in New York in 1990, Open Systems Technologies is one of the largest, privately held, staffing companies in the world. We have experienced organic growth over the past 25 years and currently employ over 1,500 consultants in 16 domestic and international markets. Through our brands of Open Systems, OST Financial, OST Legal, OST Government Services, and OST Global we strive for continued expansion and excellence in the staffing industry. With the Global Services division, starting Jan-2012, Open Systems has expanded into the ITO & BPO Projects/Solutions business.

Responsibilities:

• Design, prototype and build low-latency trading components, while integratating with existing trading platforms
• Research, design, prototype and test new libraries, new technology (hardware and software) stacks, vendor solutions, etc. in a dedicated R&D Lab
• Review architecture, application instrumentation and profiling, performance tuning recommendations, offering reference implementations where applicable
• Actively collaborate with application and infrastructure groups as required by the role

Skills:

• 7+ years of experience in low-latency C/C++ programming and Linux/UNIX background
• 5+ years of experience in low-latency and high-performance computing (preferably in financial services)
• 4+ years of experience with kernel-bypass technologies such as RDMA, DPDK, SolarFlare openOnLoad /TCPDirect/ef_vi, Mellanox VMA, etc...
• 4+ years of experience with instrumenting, benchmarking, profiling and performance tuning of applications using tools such as Intel Parallel Studio toolset, etc...
• Experience with programming to modern hardware stack, high-performance software design practices that make optimal use of underlying hardware architecture (chip design, memory/cache hierarchy, PCIe data transfers, interconnects, etc.) is highly desired
• String understanding of multithreading, parallel programming (openMP, MPI, etc.), SIMD programming, cache-friendly programming, lock-free semantics

All your information will be kept confidential according to EEO guidelines.